<?xml version="1.0"?>
<rss version="2.0">
  <channel>
    <title>Luis Cordova's Resume</title>
    <link>http://lcordova.emurse.com/</link>
    <description>Luis Cordova's Resume</description>
    <language>en-us</language>
    <generator>Emurse.com</generator>
    <item>
      <title>Luis Cordova's Current Resume as of Tuesday, January 15th 2008</title>
      <link>http://lcordova.emurse.com/</link>
      <description><![CDATA[<center><a href="http://lcordova.emurse.com/">View Luis Cordova's Complete Resume at Emurse.com</a></center><br/><CENTER>
	
	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;"><B><FONT SIZE='+1'>E</FONT>DUCATION</B>&nbsp;</P>
			</TD> 
		</TR>
		<TR >
			<TD VALIGN=TOP COLSPAN=2 ALIGN=LEFT>
				<P ALIGN=LEFT><FONT STYLE="font-size:12pt;"><U>University of South Carolina</U></FONT>, Columbia, SC</P>
			</TD>
		</TR>
		<TR>
			<TD VALIGN=TOP COLSPAN=2 ALIGN=LEFT>
				<P ALIGN=LEFT ><I>BS in Electrical Engineering</I></P>
			</TD>
			<TD VALIGN=TOP COLSPAN=2 ALIGN=LEFT>
				<P ALIGN=LEFT CLASS="entryBreak">&nbsp;</P>
			</TD>
		</TR>
	</TABLE>

</CENTER>

<CENTER>

	<TABLE   CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=319 VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:16pt;"><B><FONT SIZE='+2'>L</FONT>UIS <FONT SIZE='+2'>C</FONT>ORDOVA</B></P>
			</TD>
			<TD WIDTH=300 VALIGN=BOTTOM>
				<P ALIGN=RIGHT><B></P>
			</TD>
		</TR>
		<TR>
			<TD COLSPAN=3>
				<P ALIGN=RIGHT STYLE="border-bottom: none; border-top: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;font-size:9pt;">
				Columbia - USA
				</P>
			</TD>
		</TR>
	</TABLE>

</CENTER>

<CENTER>

	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD COLSPAN=2 WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;"><B><FONT SIZE='+1'>W</FONT>ORK <FONT SIZE='+1'>E</FONT>XPERIENCE</B>&nbsp;</P>
			</TD> 
		</TR>
		<TR >
			<TD WIDTH=369 VALIGN=TOP ALIGN=LEFT>
				<P ALIGN="LEFT"><FONT STYLE="font-size:12pt;"><U>Oak Ridge National Laboratory</U></FONT>, Oak Ridge, TN</P>
			</TD>
			<TD WIDTH=250 ALIGN=LEFT>
				<P ALIGN="RIGHT"><B>May 9th 2005 - August 3rd 2005</B></P>
			</TD>
		<TR>
			<TD COLSPAN=2 VALIGN=TOP ALIGN=LEFT>
				<I>Student Researcher</I>
			</TD>
		</TR>
		<TR>
			<TD COLSPAN=2 VALIGN=TOP WIDTH=619 ALIGN=LEFT>
				<DIV ALIGN="LEFT" >Advance FPGA architectures for high performance computing summer position of a shared collaboration between the Engineering Science and Technology Division and the Future Technologies Group, Computational Science and Mathematics Division at the Oak Ridge National Laboratory.</DIV>
				
			</TD>
		</TR>
	</TABLE>

</CENTER>

<CENTER>
	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none;padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;"><B><FONT SIZE='+1'>P</FONT>UBLICATIONS</B>&nbsp;</P>
			</TD> 
		</TR>
		
		<TR>
			<TD WIDTH=619 COLSPAN=2 ALIGN=LEFT>
				<DIV ALIGN=LEFT>1)L. E. Cordova, M. C. Smith, J. S. Vetter, and S. Alam, "A High Performance Programming Model for Large-Scale Molecular Dynamics Calculations on Reconfigurable Supercomputers," in Proc. of the High Performance Embedded Computing Conference (HPEC'05), Massachusetts, USA, September 20-22, 2005.<br>2)L. E. Cordova, and Duncan A. Buell, "A Novel High-level Dynamic Hardware-Software Remapping Technique for Mission Critical Reconfigurable Computers," in Proc. of the IEEE Military and Aerospace Programmable Logic Devices (MAPLD'05), Washington, D.C., USA, September 7-9, 2005.<br>3)L. E. Cordova, and James P. Davis, "Toward achieving molecular circuit robustness using a multi-valued programmable logic model," in Proc. of the 1st IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH'05), Palm Springs, CA, USA, May 1, 2005.<br>4)L. E. Cordova, and Ducan A. Buell, "A high-level DSP Studio for the SRC-6 reconfigurable computer," To be submitted.<br>5)L. E. Cordova, and Ducan A. Buell, "Design and implementation of a molecular dynamics program for the SRC-6E reconfigurable computer," To be submitted.<br>6)J. M. Seminario, and L. E. Cordova, "Theoretical interpretation of intrinsic line widths observed in inelastic electron tunneling scattering experiments," Journal of Physical Chemistry, 108(24), 5142 - 5144 (2004).<br>7)J. M. Seminario, P. A. Derosa, L. E. Cordova, and B. H. Bozard, "A molecular device operating at terahertz frequencies: Theoretical simulations," IEEE Trans. Nanotechnology, 3(1), 215-218 (2004).<br>8)Jorge Seminario, Pedro Derosa, Luis Cordova, and Brian Bozard, "Molecular dynamics simulations of a molecular electronics device: The NanoCell," Computational Chemistry: review of current trends, World Scientific (Book chapter).<br>9)J. M. Seminario, L. E. Cordova, and P. A. Derosa, "An ab-initio approach to the calculation of current-voltage characteristics of programmable molecular devices," Proc. IEEE, 91(11), 1958-1975 (2003).<br>10)J. M. Seminario, L. E. Cordova, and P. A. Derosa, "Search for minimum molecular programmable units," in Proc. IEEE Nanotechnology Conf., vol. 2, 2002, pp. 421-424.<br>11)J. M. Seminario, and L. E. Cordova, "Toward multiple-valued configurable random molecular logic units," in Proc. IEEE Nanotechnology Conf., vol. 1, 2001, pp. 146-150.</DIV>
			</TD>
		</TR>
	</TABLE>
</CENTER>

<CENTER>
	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;"><B><FONT SIZE=+1>R</FONT>ESEARCH</B>&nbsp;</P>
			</TD> 
		</TR>
		<TR>
			<TD WIDTH=619 COLSPAN=2 ALIGN=LEFT>
				<DIV ALIGN=LEFT>Disclosure:<br>1)Non-linear device solver of systems with multiple solutions, J. M. Seminario and L. E. Cordova, Disclosed July 2002.<br><br>Poster Presentations:<br>1)An Approach to Scalable Molecular Dynamics Simulation using Supercomputing Adaptive Processing Elements, Ph.D. Forum Presentation, 15th International Conference on Field Programmable Logic and Applications. Tampere, Finland, August 24-26.<br>2)The DARPA data transposition benchmark on a reconfigurable computer, with S. Akella, D. Buell, J. Hammes, in Proc. of the IEEE Military and Aerospace Programmable Logic Devices (MAPLD'05), Washington, D.C., USA, September 7-9, 2005.<br>3)The DARPA dynamic programming benchmark on a reconfigurable computer, with Duncan A. Buell, and S. Akella, in Proc. of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), Napa, CA, USA, April 17-20, 2005.<br>4)Molecular Electronics: Computing with atoms, TDDFT Summer School, 2004, June 5-10.<br>5)Molecular Electronics, USC Discovery Day, 2004, April 23.<br>6)Search for Minimum Molecular Programmable Units, Poster presentation, Sigma Xi Undergraduate Research Symposium 2001. Raleigh, NC, November 10.<br>7)Search for Minimum Molecular Programmable Units, Poster presentation, Computational Chemistry Undergraduate Symposium 2002. Clinton, NY, July 21-23.<br>8)Analysis of Oxygen Density States under Metallic Backgrounds, Computational Nanoscience, USC Nanocenter Symposium III 2002, November 7-9.<br>9)Molecular Programmable Circuits, Poster presentation, SERMACS 2002. Charleston, SC, November 13-16.<br>10)Towards Fast Prototyping Automation using IEEE 1532 Concurrent Programming and IEEE 1149.1 over JINI and SSH-CVS, VII Iberchip 2001. Montevideo, Uruguay, March 21-23.<br>11)Scanlet for Functional Verification of Fuzzy Logic Controllers, Jornadas de Nuevas Tecnologias y Logica Difusa 2000. Sevilla, Spain, September 22-24.<br>12)STUD: Scanlet for Test and Upgrade Design, and Fault Tolerant Circuits: Hardening Memory Elements in VHDL, Design Automation Conference 2000. Los Angeles, CA, June 5-9.<br>13)Fast Prototyping Methodology and Design Flow, V Iberchip Workshop 1999. Lima, Peru, March 1-3.<br>14)Design and Implementation of a Fuzzy Logic Controller Tuned with ANFIS Algorithm: Application, JIASE 1999. Lima, Peru, July 19-23.<br>15)Fuzzychip, InterCon 1999. Lima, Peru, August 17-20.<br>16)Fuzzy Logic Based Controller Implemented in an FPGA, VI Iberchip Workshop 2000. Sao Paulo, Brazil, March 16-18.<br><br>Travel Grants:<br>1)An Approach to Scalable Molecular Dynamics Simulation using Supercomputing Adaptive Processing Elements, Ph.D. Forum Presentation, 15th International Conference on Field Programmable Logic and Applications. Tampere, Finland, August 24-26.<br>2)Molecular Electronics: Computing with atoms, Poster presentation, TDDFT Summer School 2004. Santa Fe, NM, June 5-10.<br>3)Fuzzy Logic Controller in an FPGA, Poster presentation, Design Automation Conference 2000. Los Angeles, CA, June 5-9.<br>4)Fast Prototyping, Poster presentation, Design Automation Conference 2001. Las Vegas, NV, June 18-22. <br>5)Molecular Electronics, Poster presentation, Design Automation Conference 2002. New Orleans, LA, June 10-14.</DIV>
			</TD>
		</TR>
	</TABLE>
</CENTER>

<CENTER>
	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in;padding-left: 0in;padding-right: 0in;"><B><FONT SIZE='+1'>T</FONT>RAINING</B>&nbsp;</P>
			</TD> 
		</TR>
		<TR>
			<TD WIDTH=619 COLSPAN=2 ALIGN=LEFT>
				<DIV ALIGN=LEFT>1)JTAG Boundary-Scan Seminar, Atlanta, GA, January, 2005.<br>2)Xilinx university program workshop in DSP, Atlanta, GA, October, 2004.<br>3)Xilinx university program workshop in Embedded Systems, Atlanta, GA, October, 2004.<br>4)Avnet-Xilinx effective FPGA simulation techniques, Spartanburg, SC, April, 2004.<br>5)Time-dependent Density Functional Theory (TDDFT), Santa Fe, NM, June, 2004.<br>6)System C+ hands-on course and laboratory, New Orleans, LA, June, 2002.<br>7)Xilinx-WindRiver hands-on course and laboratory, New Orleans, LA, June, 2002.<br>8)Xilinx programmable world, Duluth, GA, March, 2002.<br>9)International course on interfacing Microsystems II, Montevideo, Uruguay, March, 2001.<br>10)Xilinx university program workshop, San Jose, CA, June, 2000.<br>11)7th Training on SoC design using design and prototyping platforms, Santa Clara, CA, June, 2000.<br>12)International course on interfacing Microsystems I, Florianopolis, Brazil, March, 2000.<br>13)International course on Analog IC Design I, Cusco, Peru, February, 1999.<br>14)Training on Programmable Logic Design using Altera Tools, Lima, Peru, April, 1999.<br>15)IC Microelectronics Design Training, Lima, Peru, February, 1999.<br>16)Training on Programmable Logic Devices, Lima, Peru, March, 1998.<br>17)Training on Industrial Programmable Logic Controllers, Lima, Peru, February, 1998.<br>18)Introductory Training on Mechatronics Systems, Lima, Peru, January, 1998.<br>19)International Conference on Automatic Control, Piura, Peru, January, 1998.<br>20) ABB Intelligent Substations Training, Lima, Peru, January, 1998.</DIV>
			</TD>
		</TR>
	</TABLE>
</CENTER>

<CENTER>
	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;"><B><FONT SIZE='+1'>C</FONT>OURSE <FONT SIZE='+1'>W</FONT>ORK</B>&nbsp;</P>
			</TD> 
		</TR>
		<TR>
			<TD WIDTH=619 COLSPAN=2 ALIGN=LEFT>
				<DIV ALIGN=LEFT >Relevant college courses and skills:<br>Digital Control Systems, Computer Architecture, Analysis of Algorithms<br>Wireless Communications<br>RF Circuit Design and Microwave Engineering<br>Advanced Semiconductor Materials<br>Digital Signal Processing, Parallel Computing, Compiler Construction<br>Physical Chemistry<br>Language learning skills, currently studying Quechua and German</DIV>
			</TD>
		</TR>
	</TABLE>
</CENTER>

<CENTER>
	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;"><B><FONT SIZE='+1'>A</FONT>WARDS <FONT SIZE='+1'>A</FONT>ND <FONT SIZE='+1'>H</FONT>ONORS&nbsp;</B></P>
			</TD> 
		</TR>
		<TR>
			<TD WIDTH=619 COLSPAN=2 ALIGN=LEFT>
				<DIV ALIGN=LEFT>Awards, Honor Scholarships, and affiliations<br>Research assistantship at the USC Reconfigurable Group since 2004<br>Research assistantship at the USC Moletronics Group (26 k US$/year) 2001-2004<br>Hubert Noland scholarship, 2002-2003<br>Joseph Biedenbach scholarship, 2004<br>USC Discovery Day 2004 First Place in Computer Science and Engineering<br>Member, IEE (Institute of Electrical Engineers), since 2004<br>Member, IEEE (Institute of Electrical and Electronics Engineers), since 1996<br>Member, Audio Engineering Society (AES), since 2004<br>Member, IEEE USC Student chapter, since 2001<br>Member, IEEE Standards Association, since 2002<br>Developer, IEEE 1532 In-System Configuration Standard, since 1999<br>Developer, IEEE 1581 Component Interconnection Test, since 2004<br>Vice President of the IEEE Professional Section of Columbia, SC, 2005<br>President of the USC AES Student Chapter, SC, 2005<br>Nominated for America's Registry of Outstanding Professionals, 2005<br>Students' affairs office recognition for outstanding academic achievement 2002<br>Dean's honors list 2002<br>Travel awards (~6k US$)</DIV>
			</TD>
		</TR>
	</TABLE>
</CENTER>

<CENTER>
	<TABLE WIDTH=619   CLASS="webTable" CELLPADDING=0 CELLSPACING=0>
		<TR>
			<TD WIDTH=100% VALIGN=TOP>
				<P ALIGN=LEFT STYLE="font-size:12pt;margin-bottom:5pt;border-top: none; border-bottom: 1px solid #000000; border-left: none; border-right: none; padding-top: 0in; padding-bottom: 0in; padding-left: 0in; padding-right: 0in;"><B><FONT SIZE='+1'>O</FONT>BJECTIVE</B>&nbsp;</P>
			</TD> 
		</TR>
		<TR>
			<TD WIDTH=619 COLSPAN=2 ALIGN=LEFT>
				<DIV ALIGN=LEFT >Reconfigurable/DSP/embedded research/application engineer part-time position<br>Interests: High performance/reconfigurable/embedded computing, digital signal processing</DIV>
			</TD>
		</TR>
	</TABLE>
</CENTER>

<br/><br/><center><a href="http://lcordova.emurse.com/">View Luis Cordova's Complete Resume at Emurse.com</a></center>]]></description>
      <pubDate>Tue, 15 Jan 2008 14:51:38 -0500</pubDate>
      <guid isPermaLink="true">http://lcordova.emurse.com/</guid>
      <category>luiscordova</category>
      <category>resume</category>
      <category>emurse</category>
    </item>
  </channel>
</rss>
